1. Field of the Invention
The invention relates to design of semiconductor chips. More specifically, the invention relates to a method and an apparatus for determining from a chip, values of one or more hardware parameters (e.g. FIFO size) that are specified when configurable intellectual property (IP) is synthesized.
2. Related Art
In the past, semiconductor companies used to design a chip and supply the chip design to another company that owns a foundry for fabrication of the chip. Later on, some semiconductor companies began to simply supply intellectual property (IP) in the form of computer files commonly called “core” to chip designers who in turn used the core in their chip design. A chip designer may integrate IP cores for several devices (such as microprocessor, memory, and peripherals) from several vendors into a single design, which is then implemented in a single chip. For this reason, the chip designer is also referred to as “core integrator” which is a different role from a “core designer” who designs the core.
IP cores were initially supplied to chip designers in a physical design form (e.g. transistor level layout such as GDSII) commonly used to manufacture chips. Later, semiconductor companies started to supply IP cores in the form of synthesizable source code (also called “soft cores”) which may be in, for example, a Hardware Description Language (HDL) such as Verilog or VHDL. Such soft cores are commonly designed by use of a tool (also called core designer's tool), such as Synopsys' CoreBuilder™. The soft cores are customized by the core integrator, normally via another tool (also called core integrator's tool), such as Synopsys' CoreConsultant™.
Typically, the core designer's tool places constraints on customizations that the core integrator may make to the original soft core. For example, only two options (16 bit and 32 bit registers) may be supported in a specific design of the soft core. The core designer's tool captures such constraints, and may also capture synthesis data, and other core designer knowledge for use in implementation/verification. Such data along with a customized soft core generated by the core integrator's tool is then compiled in synthesis tools (such as Synopsys' Design Compiler®, Test Compiler™, Power Compiler™ or PrimeTime™ software programs) to create a netlist for the user's customized design. The user then implements the netlist in a semiconductor device in the normal manner. For example, the design may be implemented in an FPGA such as XILINX VIRTEX XCV2000 or implemented in an application specific integrated circuit (ASIC) fabricated in a foundry.
After a few iterations of simulation, synthesis, implementation and testing of a design, the user may end up with multiple physical copies of the integrated circuit (IC) being designed. Each copy differs from another copy primarily in the customization done by the user. For example, the user may end up with two copies of a microcontroller, wherein one copy has a 16-bit wide register file containing 32 registers, and another copy has a 32-bit wide register file containing 16 registers (if these values were used during customization).
The inventor of the current patent application has found that when such copies become numerous (i.e. more than a couple), it can be difficult to mentally keep track of which particular copy contains hardware features of which particular values of the customizable parameters. Moreover, the inventor notes that absence of documentation confuses a new user who takes over responsibility for the development work from a user who performed the customizations and now has numerous copies. Similarly, depending on the complexity of the IP, the inventor notes that the provider of the core may want to write a single driver than can transparently be used with all of the allowable configurations by allowing the driver to identify the core and its configuration parameters.
An industry standard for adding expansion cards to personal computers called “Plug and Play” is well known in the art. This standard is commonly used to resolve conflicts that may arise as a result of different resource requirements of the expansion cards. Because all expansion cards respond to the same I/O port address, a unique number (called “serial identifier”) composed of two 32-bit fields and an 8-bit checksum is provided on each expansion card. The first 32-bit field is typically the vendor identifier, while the second 32-bit field can be any value, such as the card serial number, as long as the first and second 32-bit fields represent a number that is unique to the expansion card. U.S. Pat. No. 5,517,646, which describes this standard, is incorporated by reference herein in its entirety as background.